The complexity of integrated circuits forced designers to use various testing procedures and architectures. One common architecture and protocol is defined at IEEE standard 1149.1 that is also known as JTAG.
FIG. 1 illustrates a prior art JTAP compliant test access port (TAP) 10 and a core 11 that is connected to the TAP 10. TAP 10 includes a boundary scan register 30, a one-bit long bypass register 12, an instruction register 18, a TAP controller 20, and an optional user defined data register 14.
TAP 10 receives various signals including a clock signal TCK, a test data input signal TDI, a test mode select signal TMS and outputs a test data output signal TDO.
Various control signals provided by the TAP controller 20, especially in response to TMS signals select a path between the TDI and TDO ports of TAP 10.
The instruction register 18 forms an instruction path while each of the boundary scan register 30, bypass register 12 and the optional user defined data register 14 defines a data path. Each data path and instruction path can be regarded as an internal test path of TAP 10.
The TAP controller 20 is a state machine that is controlled by the TMS signal. FIG. 2 illustrates the multiple states of the TAP controller 20: Test logic reset 40, run-test/idle 41, select DR scan 42, capture DR 43, shift DR 44, exit1 DR 45, pause DR 46, exit2 DR 47, update DR 48, select IR scan 52, capture IR 53, shift IR 54, exit1 IR 55, pause IR 56, exit2 IR 57 and update IR 58. The stages are illustrates as boxes that are linked to each other by arrows. The arrows are accompanied by digits (either 0 or 1) that illustrate the value of the TMS signal. These stages are well known in the art and require no further explanation.
Generally, the TAP controller 20 sends control signals that allow to input information into selected data and instruction paths, to retrieve information from said paths and to serially propagate (shift) information along data and instruction paths.
Typically, the instruction register 18 includes an instruction shift register as well as a shadow latch. Signals propagate serially through the instruction shift register and are provided in parallel to the shadow latch.
The IEEE standard 1149.1 defines mandatory instructions such as BYPASS instruction that selects an internal test path that includes the one-bit long bypass register, an EXTEST instruction that causes the integrated circuit to enter an external boundary test mode, and a SAMPLE/PRELOAD instruction that selects an internal test path that includes the boundary scan register, and a EXTEST instruction that causes the TAP to enter an external boundary test mode.
The IEEE standard 1149.1 also defines optional instructions such as CLAMP instruction, HIGHZ instruction, IDCODE instruction, INTEST instruction that causes the integrated circuit to enter an internal boundary test mode, RUNBIST instruction that causes the integrated circuit to enter a self test mode, and USERCODE instruction that selects an internal test path that includes an ID register.
The IEEE standard 1149.1 is suited for single core integrated circuits. The adaptation of that standard to multi-core integrated circuits such as system on chips is not trivial. For example, such an adaptation requires a provision of a one-bit long bypass register even if multiple TAP controllers exist within a single integrated circuit.
Various examples to adapt the IEEE standard 1149.1 to multiple core integrated circuits are known in the art. Some are described in U.S. Pat. No. 6,073,254 of Whetsel and U.S. Pat. No. 6,311,302 of Cassetti et al., both incorporated herein by reference.
One prior art for testing a multiple TAP integrated circuit is to provide a test path by selectively linking one or more TAPs between the TDI and TDO pins of an integrated circuit. This results in varying the length of the test path, and complicates the testing procedure, due to the need to adapt to timing variations resulting from the differing test path length. Said adjustments complicate re-using existing software modules and complicates the testing procedure.
There is a need to provide a method and apparatus for testing a multiple TAP system.